The invention relates to a design method and a design system for semiconductor integrated circuits, and particularly relates to a design method and a design system for semiconductor integrated circuits permitting realization of a minimum machine cycle while minimizing the number of man-hours and the amount of changes of physical design and modifications of packaging design.
As a prior art pertaining to a method for adjusting the clock timing of flip-flops to reduce machine cycles, for example, a technology is known which is described in A. TAKAHASHI AND Y. KAJITANI, “PERFORMANCE AND RELIABILITY DRIVEN CLOCK SCHEDULING OF SEQUENTIAL LOGIC CIRCUITS,” IN PROC. ASP-DAC '97, PP. 37 to 42, 1997. In this first prior art, when flip-flop-to-flip-flop signal propagation delay time (hereinafter, referred to as a path delay) is given, timing of a clock signal inputting to each flip-flop can be changed within the range in which the timing can be changed by using signal propagation in the flip-flop-to-flip-flop signal propagation path (hereinafter, referred to as a path), thereby enabling the clock period to be made shorter than the maximum value of the signal delay time of the path.
Also, as a prior art pertaining to a method of adjusting clock timing of flip-flops, there is known a technology reported by “Schedule-Clock-Tree Routing for Semi-Synchronous Circuits” (PP. 54 to 61) in “CAD21 result report of the fiscal year 1998” (TOKYO Institute of Technology CAD21 Research Body), for example. In this second prior art, with respect to the algorithm of so-called ZERO-SKEW CLOCK-TREE ROUTING, when a difference of clock timing exists between two flip-flops, cost is defined as the length of detour wiring needed for adjusting the delay difference and an increment in wiring length by connecting a flip-flop that is at remote distance but has a small difference of clock timing. Then, two flip-flops making this cost minimum are coupled. Herein, in the algorithm of ZERO-SKEW CLOCK-TREE ROUTING, two flip-flops located at the shortest distance are coupled, and then connected to a clock source pin that is at the distance shortest from a set of midpoints between the coupled flip-flops.